VLSI Positions_Hyderbad location

3 - 8 Years

Job Description

Please share your resume and details on fitment:
Exp band: 4-11 Years
Work Location: Hyderbad
REQ #1

Job Description:

SOC Verification Engineer
Development of verification plans
Verification environments

Test cases and ensuring coverage and performance goals are achieved for IP and SOC level
HVLs/Tools: SV, UVM, C
Domain: Networking, DDR2/3/4, Ethernet PCIe,

IP Verification Engineer
Job Description:
4 - 10 years experience in Design Verification
Strong System Verilog or Specman expertise OVM/UVM/eRM expertise highly desired
Good knowledge of protocols
Ability and desire to learn new methodologies, languages, protocols etc

Design Verification, System Verilog or Specman expertise OVM/UVM/eRM

RTL Design Engineer :Verilog/VHDL, DC-Compiler, Prime time, PTPX, Power-Artist, LEC

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Salary: Not Disclosed by Recruiter

Industry:Semiconductors / Electronics

Functional Area:IT Software - Embedded, EDA, VLSI, ASIC, Chip Design

Role Category:Programming & Design

Role:Team Lead/Technical Lead

Employment Type:Permanent Job, Full Time

Key Skills

Desired Candidate Profile

Please refer to the Job description above

Company Profile

Kaizen SRA Technologies Pvt. Ltd.
Kaizen SRA Technologies Pvt. Ltd.
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Contact Company:Kaizen SRA Technologies Pvt. Ltd.

Email :sureshm@kaizentek.com